This invention relates to a charge-coupled device (CCD) with enhanced output dynamic range.
FIG. 1 illustrates schematically the readout section 2 of a conventional 3-phase CCD. The readout section 2 includes a serial register 4 implemented by a segment of a channel of N conductivity formed in a die of P-type silicon. The serial register 4 has several stages 6. Three of the stages, designated 61, 62 and 63 respectively, are shown in FIG. 1. A gate structure, illustrated in FIG. 1 as a 3-phase gate structure, overlies the serial register and functionally divides each stage of the serial register into three cells. The three cells of a given stage of the serial register are referred to herein as cells 1, 2 and 3 respectively, in accordance with the phase of the gate structure overlying the cells. The 3-phase gate structure is connected to a clock generator 14 which can be controlled to generate a 3-phase clock signal.
FIG. 1 also shows an N+ floating diffusion 8 and an N+ reset diffusion 10. The floating diffusion 8 is connected to the gate of an on-chip charge sensing amplifier, which may be a MOSFET source follower 16. The source of the MOSFET is connected to a signal chain 24, which includes an A/D converter 28 and provides a digital output signal to a signal processor 32. The reset diffusion 10 is connected to a predetermined reference potential VR. A summing well 12, controlled by a summing gate SG, is between the serial register 4 and the floating diffusion 8. The summing gate SG is located between the last stage of the 3-phase gate structure and a last gate LG. The summing gate SG is driven by a summing gate driver 18 between high and low clocking levels VH and VL and the last gate LG is held at a voltage VLG which is slightly more positive than VL. A reset gate RG overlies the region of the channel between the floating diffusion 8 and the reset diffusion.
In operation of the readout section shown in FIG. 1, charge packets are introduced into the different stages 6 of the serial register. The charge packets may be formed in a sensing region of the device and shifted from the sensing region into the serial register. Typically, the clock generator 14 holds phases 1 and 2 of the gate structure high and phase 3 low when the charge packets are shifted into the serial register, so that a charge packet is held in cells 1 and 2 of stage 6i of the shift register while cell 3 provides a barrier between the charge packet in stage 6i and the packet in cells 1 and 2 of stage 6ixe2x88x921 of the serial register. During this phase of operation, the summing gate and the reset gate will typically be low. When the charge packets have been shifted into the respective stages of the serial register, the clock generator 14 applies the 3-phase clock signal to the 3-phase gate structure and the charge packets are shifted from left to right in FIG. 1. The summing gate driver 18 clocks the summing gate SG high and the charge packet from the last stage 61 of the serial register is shifted into the summing well 12. The potential of the last gate LG, being lower than the potential of the summing gate SG, provides a barrier retaining the charge packet in the summing well 12. Subsequently, the summing gate SG is driven low and the charge packet moves past the last gate LG into the floating diffusion 8. Prior to shifting the charge packet into the floating diffusion, the reset gate RG is driven high thereby connecting the floating diffusion to the reset diffusion 10. The reset gate is then driven low. In this manner, the floating diffusion is set to the reference potential VR and is then isolated from the reset diffusion 10.
When the charge packet enters the floating diffusion 8 from the summing well, the voltage of the floating diffusion changes by an amount that depends on the size of the charge packet. The MOSFET 16 generates an output voltage change which depends on the potential change of the floating diffusion and hence on the size of the charge packet in the floating diffusion. The signal chain 24 provides a digital output signal that depends on the output voltage change of the MOSFET 16.
After the charge packet has been sensed by the MOSFET 16, the reset gate RG is driven sequentially high and low, setting the floating diffusion 8 to the reference potential VR as before.
The size of the charge packets delivered to the floating diffusion in a CCD of the kind shown in FIG. 1 varies over a wide dynamic range. It is desirable that the signal chain be able to measure a small packet with a high degree of precision and that it also be able to measure a large packet.
The dynamic range of the packet size that can be measured depends on the number of bits that can be quantized by the A/D converter 28. If the A/D converter is able to quantize to 10 bits and the voltage of the least significant bit of the digital signal generated by the A/D converter corresponds to the read noise Vn, the dynamic range of the packet size that can be measured is 2{circumflex over ( )}10. It would be desirable to have a wider dynamic range in some applications.
The sensitivity of the output amplifier structure composed of the floating diffusion 8 and the MOSFET 16 is typically measured in terms of the change in output voltage per unit of signal charge supplied to the floating diffusion 8. The voltage change sensed by the MOSFET is given by q/C, where q is the size of the charge packet and C is the capacitance seen by the charge packet entering the floating diffusion. Therefore, an important parameter in determining the sensitivity of the output amplifier structure is the capacitance seen by the charge packet entering the floating diffusion. For example, if the voltage gain of the MOSFET is unity and the charge packet sees a capacitance of 0.1 pF, the sensitivity is 1.6 microvolts per electron. Sensitivity values of from 0.5 microvolts per electron to more than 10 microvolts per electron are common.
Since the sensitivity of the output amplifier structure depends on the capacitance seen by a charge packet entering the floating diffusion, the sensitivity can be selectively reduced, and the dynamic range selectively increased, by increasing the capacitance seen by the charge packet entering the floating diffusion.
In accordance with a first aspect of the invention there is provided a CCD having a floating diffusion for receiving charge packets to be sensed, a reset diffusion connected to a reference potential level, a reset channel region between the floating diffusion and the reset diffusion, a first reset gate positioned over a first segment of the reset channel region for controlling conductivity of said first segment in accordance with potential of the first reset gate, and a second reset gate positioned over a second segment of the reset channel region between the first reset gate and the reset diffusion for controlling conductivity of said second segment in accordance with potential of the second reset gate, each reset gate having a first state in which the respective segment of the reset channel region is conductive and a second state in which the respective segment of the reset channel region is not conductive, whereby a charge packet entering the floating diffusion sees a relatively small effective capacitance when the first reset gate is in the second state and sees a relatively large effective capacitance when the first reset gate is in the first state and the second reset gate is in the second state, and the CCD also having a reset gate controller for dynamically controlling the states of the first and second reset gates in accordance with predicted size of a charge packet entering the floating diffusion.
In accordance with a second aspect of the invention there is provided a CCD having a floating diffusion for receiving charge packets to be sensed, a reset diffusion connected to a reference potential level, a reset channel region between the floating diffusion and the reset diffusion, a reset gate positioned over the reset channel region for controlling conductivity of the reset channel region in accordance with potential of the reset gate, an auxiliary channel region connected at one end to the floating diffusion, an auxiliary gate positioned over the auxiliary channel region for controlling conductivity of the auxiliary channel region in accordance with potential of the auxiliary gate, each gate having a first state in which the respective channel region is conductive and a second state in which the respective channel region is not conductive, whereby a charge packet entering the floating diffusion sees a relatively small effective capacitance when the auxiliary gate and the reset gate are each in the second state and sees a relatively large effective capacitance when the auxiliary gate is in the first state and the reset gate is in the second state, and the CCD also having a reset gate controller for dynamically controlling the states of the reset gate and the auxiliary gate in accordance with predicted size of a charge packet entering the floating diffusion.
In accordance with a third aspect of the invention there is provided a CCD having a floating diffusion for receiving charge packets to be sensed, a read-ahead well through which a charge packet passes in transit to the floating diffusion, and a circuit in operative connection with the read-ahead well to generate a signal dependent on the size of a charge packet in the read-ahead well.
In accordance with a fourth aspect of the invention there is provided a method of operating a CCD having a floating diffusion for receiving charge packets to be sensed and an output amplifier with an input coupled to the floating diffusion for generating an output signal that depends on the size of a charge packet in the floating diffusion with a sensitivity that depends on the capacitance seen by the charge packet when entering the floating diffusion, the method comprising adjusting the capacitance seen by the charge packet depending on the size of the charge packet.